In the Back-End-of-Line (BEOL) stage of semiconductor manufacturing and wafer pre-shipment (CP) testing, insulation layer quality directly determines chip yield and long-term reliability. After multi-layer metal routing and passivation treatment (such as PSG, BPSG), complex capacitance and resistance structures form between metal layers and between metal layers and the silicon substrate.
1. Test Requirements
1. Interlayer Insulation Evaluation
Detect the insulation resistance between adjacent metal routing layers and screen micro-shorts caused by incomplete etching or particle contamination.
2. Passivation Layer Withstand Voltage and Leakage Current Testing
Evaluate the integrity of the wafer surface passivation layer and measure its leakage current and insulation resistance under specific bias to prevent potential breakdown risks.
3. High-Speed Testing
Wafer testing faces enormous capacity pressure, and traditional single-channel testing cannot meet throughput requirements, so equipment supporting high-speed testing is needed.

